High performance logic device structures often include embedded SiGe channels in the pFETs while the nFETs are constructed on conventional single crystal substrates. To construct multiple gate oxides (so called double gate architectures) on embedded SiGe channels and on Si channels requires that the gate insulators/dielectrics be deposited, for example, by means of chemical vapor deposition (CVD). CVD techniques are used in order to construct devices with comparable physical thicknesses. If the double gate oxides are constructed by means of thermal oxidation (in a manner consistent with non-SiGe channel technologies), then the differing oxidation rates of the SiGe and Si will result in devices with different characteristics (Tinv, Vt, Ion/Ioff etc.). These different characteristics are often problematic.
In most cases, the CVD oxides deposited on SiGe channels are so called “high temperature oxides” or HTOs. HTOs can be deposited in either single wafer or batch furnace type tools. HTOs are typically produced through a reaction of SiH4 or Si2H6 with N2O, O2 or H2O at reduced pressures such as 200 Torr and temperatures between 600° C. and 800° C.
It is often reported that HTO layers are of lower quality when compared to SiO2 films (layers) produced by means of thermal oxidation of single crystal substrates. The lower film quality is manifested in higher trap densities (in the bulk of the film and the interface) which often leads to reduced reliability metrics, e.g. Vbd, TDDB, NBTI, etc. This reduced reliability, therefore, generally precludes the use of HTOs in high performance CMOS transistor applications.